A low-capacitance contact to a source-drain contact in a multiple fin field effect transistor may be a vertical structure that does not extend along the entire length of the merged source-drain structure (consisting of the source-drain regions for the respective fins of the transistor). Related art processes for fabricating self-aligned source-drain (SD) contacts with low parasitic capacitance may expose the gate spacers (which may be composed of nitride) to an oxide etch twice: first for the opening of the long SD contact trench used to form a metal layer on the SD structures, and second for the opening of the shorter SD contact trench used for forming a vertical contact to the metal layer. Marginal etch selectivity of the dielectric SD contact trench fill (e.g. oxide) to gate spacer (e.g. nitride), may result in a risk of damaging the spacers.
Thus, there is a need for an improved method for forming low parasitic capacitance source and drain contacts.